On Tue, 31 Aug 2021 at 09:29, Shuuichirou Ishii
wrote:
>
> This is the v6 patch series.
>
> v6:
> For patch 1[1/3], added the commit messages that the Identification registers
> value are defined based on FX700, and has been tested and confirmed.
Applied to target-arm.next. Thanks!
-- PMM
This is the v6 patch series.
v6:
For patch 1[1/3], added the commit messages that the Identification registers
value are defined based on FX700, and has been tested and confirmed.
v5:
A64FX supports only 128, 256, and 512bit SVE vector lengths,
but the QEMU implementation prior to v4 did not
