On 7/20/22 21:34, Janis Schoetterl-Glausch wrote:
On 6/20/22 16:03, Pierre Morel wrote:
The handling of STSI is enhanced with the interception of the
function code 15 for storing CPU topology.
Using the objects built during the plugging of CPU, we build the
SYSIB 15_1_x structures.
With
On 6/20/22 16:03, Pierre Morel wrote:
> The handling of STSI is enhanced with the interception of the
> function code 15 for storing CPU topology.
>
> Using the objects built during the plugging of CPU, we build the
> SYSIB 15_1_x structures.
>
> With this patch the maximum MNEST level is 2,
On 6/27/22 16:26, Janosch Frank wrote:
On 6/20/22 16:03, Pierre Morel wrote:
s390x/cpu_topology: Add STSI function code 15 handling
OK
The handling of STSI is enhanced with the interception of the
function code 15 for storing CPU topology.
s/interception/handling/
OK
Using the
On 6/20/22 16:03, Pierre Morel wrote:
s390x/cpu_topology: Add STSI function code 15 handling
The handling of STSI is enhanced with the interception of the
function code 15 for storing CPU topology.
s/interception/handling/
Using the objects built during the plugging of CPU, we build the
The handling of STSI is enhanced with the interception of the
function code 15 for storing CPU topology.
Using the objects built during the plugging of CPU, we build the
SYSIB 15_1_x structures.
With this patch the maximum MNEST level is 2, this is also
the only level allowed and only SYSIB
