Re: [PATCH v8 1/3] hw/ppc: Add pnv nest pervasive common chiplet model

2023-12-12 Thread Cédric Le Goater
On 12/8/23 16:19, Chalapathi V wrote: A POWER10 chip is divided into logical units called chiplets. Chiplets are broadly divided into "core chiplets" (with the processor cores) and "nest chiplets" (with everything else). Each chiplet has an attachment to the pervasive bus (PIB) and with

[PATCH v8 1/3] hw/ppc: Add pnv nest pervasive common chiplet model

2023-12-08 Thread Chalapathi V
A POWER10 chip is divided into logical units called chiplets. Chiplets are broadly divided into "core chiplets" (with the processor cores) and "nest chiplets" (with everything else). Each chiplet has an attachment to the pervasive bus (PIB) and with chiplet-specific registers. All nest chiplets

[PATCH v8 1/3] hw/ppc: Add pnv nest pervasive common chiplet model

2023-12-08 Thread Chalapathi V
A POWER10 chip is divided into logical units called chiplets. Chiplets are broadly divided into "core chiplets" (with the processor cores) and "nest chiplets" (with everything else). Each chiplet has an attachment to the pervasive bus (PIB) and with chiplet-specific registers. All nest chiplets