The cache operation is encoded in bits [20:18] of the instruction. The 'op' argument of helper_cache() contains the bits [20:16]. Extract the 3 bits and parse them using a switch case. This allow us to handle multiple cache types (the cache type is encoded in bits [17:16]).
Previously the if() block was only checking the D-Cache (Primary Data or Unified Primary). Now we also handle the I-Cache (Primary Instruction), S-Cache (Secondary) and T-Cache (Terciary). Reported-by: Jiaxun Yang <jiaxun.y...@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.y...@flygoat.com> Message-Id: <20200813181527.22551-2-f4...@amsat.org> --- target/mips/op_helper.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 9552b280e07..c15f5c07761 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1574,15 +1574,20 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) { #ifndef CONFIG_USER_ONLY + uint32_t cache_operation = extract32(op, 2, 3); target_ulong index = addr & 0x1fffffff; - if (op == 9) { - /* Index Store Tag */ + + switch (cache_operation) { + case 0b010: /* Index Store Tag */ memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, MO_64, MEMTXATTRS_UNSPECIFIED); - } else if (op == 5) { - /* Index Load Tag */ + break; + case 0b001: /* Index Load Tag */ memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, MO_64, MEMTXATTRS_UNSPECIFIED); + break; + default: + break; } #endif } -- 2.26.2