On 7/7/20 7:26 AM, LIU Zhiwei wrote:
> As there are not only the atomic instructions have this question, all
> instructions that use
> GEN_VEXT_TRANS have the same question too. It's some difficult to address this
> question by this way.
Oh yes, I missed that. Ok, perhaps the simpler assert
On 2020/7/7 4:48, Richard Henderson wrote:
On 7/5/20 11:20 AM, Peter Maydell wrote:
On Thu, 2 Jul 2020 at 17:33, Alistair Francis wrote:
From: LIU Zhiwei
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same
On 2020/7/7 7:36, Alistair Francis wrote:
On Sun, Jul 5, 2020 at 11:20 AM Peter Maydell wrote:
On Thu, 2 Jul 2020 at 17:33, Alistair Francis wrote:
From: LIU Zhiwei
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions
On Sun, Jul 5, 2020 at 11:20 AM Peter Maydell wrote:
>
> On Thu, 2 Jul 2020 at 17:33, Alistair Francis
> wrote:
> >
> > From: LIU Zhiwei
> >
> > Vector AMOs operate as if aq and rl bits were zero on each element
> > with regard to ordering relative to other instructions in the same hart.
> >
On 7/5/20 11:20 AM, Peter Maydell wrote:
> On Thu, 2 Jul 2020 at 17:33, Alistair Francis
> wrote:
>>
>> From: LIU Zhiwei
>>
>> Vector AMOs operate as if aq and rl bits were zero on each element
>> with regard to ordering relative to other instructions in the same hart.
>> Vector AMOs provide no
On Thu, 2 Jul 2020 at 17:33, Alistair Francis wrote:
>
> From: LIU Zhiwei
>
> Vector AMOs operate as if aq and rl bits were zero on each element
> with regard to ordering relative to other instructions in the same hart.
> Vector AMOs provide no ordering guarantee between element operations
> in
From: LIU Zhiwei
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
