Re: [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs

2007-11-04 Thread Blue Swirl
On 11/4/07, J. Mayer <[EMAIL PROTECTED]> wrote: > > On Sun, 2007-11-04 at 09:12 +0200, Blue Swirl wrote: > > On 11/4/07, Fabrice Bellard <[EMAIL PROTECTED]> wrote: > > > Blue Swirl wrote: > > > > Hi, > > > > > > > > RISC CPUs don't support self-modifying code unless the affected area > > > > is flu

Re: [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs

2007-11-03 Thread J. Mayer
On Sun, 2007-11-04 at 09:12 +0200, Blue Swirl wrote: > On 11/4/07, Fabrice Bellard <[EMAIL PROTECTED]> wrote: > > Blue Swirl wrote: > > > Hi, > > > > > > RISC CPUs don't support self-modifying code unless the affected area > > > is flushed explicitly. This patch disables the extra effort for SMC.

Re: [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs

2007-11-03 Thread Blue Swirl
On 11/4/07, Fabrice Bellard <[EMAIL PROTECTED]> wrote: > Blue Swirl wrote: > > Hi, > > > > RISC CPUs don't support self-modifying code unless the affected area > > is flushed explicitly. This patch disables the extra effort for SMC. > > The changes in this version would affect all CPUs except x86,

Re: [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs

2007-11-03 Thread Paul Brook
> RISC CPUs don't support self-modifying code unless the affected area > is flushed explicitly. For experience with ARM cpus, I think this is only true for userspace. Many CPUs only require explicit flushes when the icache is enabled. It's not uncommon for bootloaders to leave the icache disabl

Re: [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs

2007-11-03 Thread Fabrice Bellard
Blue Swirl wrote: > Hi, > > RISC CPUs don't support self-modifying code unless the affected area > is flushed explicitly. This patch disables the extra effort for SMC. > The changes in this version would affect all CPUs except x86, but I'd > like to see if there are problems with some target, so t

Re: [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs

2007-11-03 Thread Thiemo Seufer
Blue Swirl wrote: > Hi, > > RISC CPUs don't support self-modifying code unless the affected area > is flushed explicitly. Not entirely true. There are cacheless MIPS CPUs (the m4k), and also cache-snooping MIPS CPUs (the R1x000). > This patch disables the extra effort for SMC. > The changes in t

[Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs

2007-11-03 Thread Blue Swirl
Hi, RISC CPUs don't support self-modifying code unless the affected area is flushed explicitly. This patch disables the extra effort for SMC. The changes in this version would affect all CPUs except x86, but I'd like to see if there are problems with some target, so that the committed change can b