On Fri, Jan 4, 2019 at 3:10 PM Peter Maydell wrote:
> On Sun, 9 Dec 2018 at 19:37, Philippe Mathieu-Daudé wrote:
> > From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and:
> >
> > 7. System Control
> > 7.1. Overview
> >
> > A10 embeds a high-speed SRAM which has been split into fi
On Sun, 9 Dec 2018 at 19:37, Philippe Mathieu-Daudé wrote:
>
> From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and:
>
> 7. System Control
> 7.1. Overview
>
> A10 embeds a high-speed SRAM which has been split into five segments.
> See detailed memory mapping in following table:
>From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and:
7. System Control
7.1. Overview
A10 embeds a high-speed SRAM which has been split into five segments.
See detailed memory mapping in following table:
Area AddressSize (Bytes)
A10x-0x3F