Thanks for all your help and I'm glad to contribute.
Seth
On Tue, Nov 20, 2018 at 12:15 PM Alistair Francis
wrote:
> On Mon, Nov 19, 2018 at 3:35 AM Philippe Mathieu-Daudé
> wrote:
> >
> > On Mon, Nov 19, 2018 at 12:08 PM Peter Maydell
> wrote:
> > > On 19 November 2018 at 10:43, Philippe
On Mon, Nov 19, 2018 at 3:35 AM Philippe Mathieu-Daudé wrote:
>
> On Mon, Nov 19, 2018 at 12:08 PM Peter Maydell
> wrote:
> > On 19 November 2018 at 10:43, Philippe Mathieu-Daudé
> > wrote:
> > > Hi Seth,
> > >
> > > On Mon, Nov 19, 2018 at 4:17 AM Seth K wrote:
> > >>
> > >> From: Seth
On Mon, Nov 19, 2018 at 12:08 PM Peter Maydell wrote:
> On 19 November 2018 at 10:43, Philippe Mathieu-Daudé wrote:
> > Hi Seth,
> >
> > On Mon, Nov 19, 2018 at 4:17 AM Seth K wrote:
> >>
> >> From: Seth Kintigh
> >>
> >> I corrected these 2 memory regions based on specifications from the chip
On 19 November 2018 at 10:43, Philippe Mathieu-Daudé wrote:
> Hi Seth,
>
> On Mon, Nov 19, 2018 at 4:17 AM Seth K wrote:
>>
>> From: Seth Kintigh
>>
>> I corrected these 2 memory regions based on specifications from the chip
>> manufacturer. The existing ranges seem to overlap and and cause odd
Hi Seth,
On Mon, Nov 19, 2018 at 4:17 AM Seth K wrote:
>
> From: Seth Kintigh
>
> I corrected these 2 memory regions based on specifications from the chip
> manufacturer. The existing ranges seem to overlap and and cause odd
> behavior and/or crashes when trying to set up multiple UARTs,
>
>
From: Seth Kintigh
I corrected these 2 memory regions based on specifications from the chip
manufacturer. The existing ranges seem to overlap and and cause odd
behavior and/or crashes when trying to set up multiple UARTs,
Signed-off-by: Seth Kintigh
---
Phil, I hope this is the right format.
