On Thu, Jun 28, 2018 at 10:14:53PM +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2018-06-28 at 10:00 +0200, Andrea Bolognani wrote:
> > On Thu, 2018-06-28 at 13:59 +1000, David Gibson wrote:
> > > On Wed, Jun 27, 2018 at 12:22:31PM +0200, Andrea Bolognani wrote:
> > > > On Tue, 2018-06-26 at
On 06/28/2018 01:40 PM, Andrea Bolognani wrote:
> On Thu, 2018-06-28 at 12:04 +0200, Cédric Le Goater wrote:
>> On 06/28/2018 10:00 AM, Andrea Bolognani wrote:
>>> On Thu, 2018-06-28 at 13:59 +1000, David Gibson wrote:
Well.. sure.. but it doesn't. pSeries is a virtual platform, so we
On Thu, 2018-06-28 at 10:00 +0200, Andrea Bolognani wrote:
> On Thu, 2018-06-28 at 13:59 +1000, David Gibson wrote:
> > On Wed, Jun 27, 2018 at 12:22:31PM +0200, Andrea Bolognani wrote:
> > > On Tue, 2018-06-26 at 19:02 +0200, Cédric Le Goater wrote:
> > > > I didn't follow that discussion but
On 06/28/2018 01:40 PM, Andrea Bolognani wrote:
> On Thu, 2018-06-28 at 12:04 +0200, Cédric Le Goater wrote:
>> On 06/28/2018 10:00 AM, Andrea Bolognani wrote:
>>> On Thu, 2018-06-28 at 13:59 +1000, David Gibson wrote:
Well.. sure.. but it doesn't. pSeries is a virtual platform, so we
On Thu, 2018-06-28 at 12:04 +0200, Cédric Le Goater wrote:
> On 06/28/2018 10:00 AM, Andrea Bolognani wrote:
> > On Thu, 2018-06-28 at 13:59 +1000, David Gibson wrote:
> > > Well.. sure.. but it doesn't. pSeries is a virtual platform, so we
> > > have a reasonable amount of flexibility to define
On 06/28/2018 10:00 AM, Andrea Bolognani wrote:
> On Thu, 2018-06-28 at 13:59 +1000, David Gibson wrote:
>> On Wed, Jun 27, 2018 at 12:22:31PM +0200, Andrea Bolognani wrote:
>>> On Tue, 2018-06-26 at 19:02 +0200, Cédric Le Goater wrote:
I didn't follow that discussion but this is "another"
On Thu, 2018-06-28 at 13:59 +1000, David Gibson wrote:
> On Wed, Jun 27, 2018 at 12:22:31PM +0200, Andrea Bolognani wrote:
> > On Tue, 2018-06-26 at 19:02 +0200, Cédric Le Goater wrote:
> > > I didn't follow that discussion but this is "another" kind of PHB.
> > > This one models the baremetal
On Wed, Jun 27, 2018 at 12:22:31PM +0200, Andrea Bolognani wrote:
> On Tue, 2018-06-26 at 19:02 +0200, Cédric Le Goater wrote:
> > On 06/26/2018 05:57 PM, Andrea Bolognani wrote:
> > > On Tue, 2018-06-26 at 15:59 +0200, Cédric Le Goater wrote:
> > > > This is a model of the PCIe host bridge found
On 06/27/2018 02:18 PM, Cédric Le Goater wrote:
> On 06/27/2018 12:22 PM, Andrea Bolognani wrote:
>> On Tue, 2018-06-26 at 19:02 +0200, Cédric Le Goater wrote:
>>> On 06/26/2018 05:57 PM, Andrea Bolognani wrote:
On Tue, 2018-06-26 at 15:59 +0200, Cédric Le Goater wrote:
> This is a model
On 06/27/2018 12:40 PM, Andrea Bolognani wrote:
> On Wed, 2018-06-27 at 18:41 +1000, Benjamin Herrenschmidt wrote:
>> On Wed, 2018-06-27 at 09:46 +0200, Cédric Le Goater wrote:
>>> So the "IBM PHB3 PCIE Root Port" is already user createable.
>>>
>>> I can take a look at user createable PHB3s. I
On 06/27/2018 12:22 PM, Andrea Bolognani wrote:
> On Tue, 2018-06-26 at 19:02 +0200, Cédric Le Goater wrote:
>> On 06/26/2018 05:57 PM, Andrea Bolognani wrote:
>>> On Tue, 2018-06-26 at 15:59 +0200, Cédric Le Goater wrote:
This is a model of the PCIe host bridge found on Power8 chips,
On 06/27/2018 10:41 AM, Benjamin Herrenschmidt wrote:
> On Wed, 2018-06-27 at 09:46 +0200, Cédric Le Goater wrote:
>> So the "IBM PHB3 PCIE Root Port" is already user createable.
>>
>> I can take a look at user createable PHB3s. I think this is OK from a model
>> perspective. The object is rather
On Wed, 2018-06-27 at 18:41 +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2018-06-27 at 09:46 +0200, Cédric Le Goater wrote:
> > So the "IBM PHB3 PCIE Root Port" is already user createable.
> >
> > I can take a look at user createable PHB3s. I think this is OK from a model
> > perspective. The
On Tue, 2018-06-26 at 19:02 +0200, Cédric Le Goater wrote:
> On 06/26/2018 05:57 PM, Andrea Bolognani wrote:
> > On Tue, 2018-06-26 at 15:59 +0200, Cédric Le Goater wrote:
> > > This is a model of the PCIe host bridge found on Power8 chips,
> > > including PowerBus logic interface, IOMMU support,
On Wed, 2018-06-27 at 09:46 +0200, Cédric Le Goater wrote:
> So the "IBM PHB3 PCIE Root Port" is already user createable.
>
> I can take a look at user createable PHB3s. I think this is OK from a model
> perspective. The object is rather standalone, it needs the machine for
> the XICS fabric and
On 06/27/2018 09:28 AM, David Gibson wrote:
> On Wed, Jun 27, 2018 at 11:38:17AM +1000, Benjamin Herrenschmidt wrote:
>> On Wed, 2018-06-27 at 03:35 +0300, Michael S. Tsirkin wrote:
>>>
+
+/* Extract field fname from val */
+#define GETFIELD(fname, val)\
+
On Wed, Jun 27, 2018 at 11:38:17AM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2018-06-27 at 03:35 +0300, Michael S. Tsirkin wrote:
> >
> > > +
> > > +/* Extract field fname from val */
> > > +#define GETFIELD(fname, val)\
> > > +(((val) & fname##_MASK) >>
On Wed, Jun 27, 2018 at 11:38:17AM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2018-06-27 at 03:35 +0300, Michael S. Tsirkin wrote:
> >
> > > +
> > > +/* Extract field fname from val */
> > > +#define GETFIELD(fname, val)\
> > > +(((val) & fname##_MASK) >>
On Wed, 2018-06-27 at 03:35 +0300, Michael S. Tsirkin wrote:
>
> > +
> > +/* Extract field fname from val */
> > +#define GETFIELD(fname, val)\
> > +(((val) & fname##_MASK) >> fname##_LSH)
> > +
> > +/* Set field fname of oval to fval
> > + * NOTE: oval isn't modified,
On Tue, Jun 26, 2018 at 03:59:28PM +0200, Cédric Le Goater wrote:
> diff --git a/include/hw/pci-host/pnv_phb3_regs.h
> b/include/hw/pci-host/pnv_phb3_regs.h
> new file mode 100644
> index ..a1672726b908
> --- /dev/null
> +++ b/include/hw/pci-host/pnv_phb3_regs.h
> @@ -0,0 +1,510 @@
>
On Tue, 2018-06-26 at 17:57 +0200, Andrea Bolognani wrote:
> On Tue, 2018-06-26 at 15:59 +0200, Cédric Le Goater wrote:
> > This is a model of the PCIe host bridge found on Power8 chips,
> > including PowerBus logic interface, IOMMU support, PCIe root complex,
> > XICS MSI and LSI interrupt
On 06/26/2018 05:57 PM, Andrea Bolognani wrote:
> On Tue, 2018-06-26 at 15:59 +0200, Cédric Le Goater wrote:
>> This is a model of the PCIe host bridge found on Power8 chips,
>> including PowerBus logic interface, IOMMU support, PCIe root complex,
>> XICS MSI and LSI interrupt sources.
>>
>> 4
On Tue, 2018-06-26 at 15:59 +0200, Cédric Le Goater wrote:
> This is a model of the PCIe host bridge found on Power8 chips,
> including PowerBus logic interface, IOMMU support, PCIe root complex,
> XICS MSI and LSI interrupt sources.
>
> 4 PHBs are provisioned under the Power8 chip model to fit
From: Benjamin Herrenschmidt
This is a model of the PCIe host bridge found on Power8 chips,
including PowerBus logic interface, IOMMU support, PCIe root complex,
XICS MSI and LSI interrupt sources.
4 PHBs are provisioned under the Power8 chip model to fit hardware but
only one is currently
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