Re: [Qemu-devel] [PATCH] ppc: Add support for 'mffsce' instruction

2019-09-15 Thread David Gibson
On Sat, Sep 14, 2019 at 01:00:21PM -0400, Richard Henderson wrote: > On 9/12/19 8:54 AM, Paul A. Clarke wrote: > > From: "Paul A. Clarke" > > > > ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) > > instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. >

Re: [Qemu-devel] [PATCH] ppc: Add support for 'mffsce' instruction

2019-09-14 Thread Richard Henderson
On 9/12/19 8:54 AM, Paul A. Clarke wrote: > From: "Paul A. Clarke" > > ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) > instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. > This patch adds support for 'mffsce' instruction. > > 'mffsce' is identical

[Qemu-devel] [PATCH] ppc: Add support for 'mffsce' instruction

2019-09-12 Thread Paul A. Clarke
From: "Paul A. Clarke" ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. This patch adds support for 'mffsce' instruction. 'mffsce' is identical to 'mffs', except that it also clears the exception