lower interrupt during chip reset. Otherwise the ESP_RSTAT register may get out of sync with the IRQ line status. This effect became visible after commit 65899fe3
Signed-off-by: Artyom Tarasenko <atar4q...@gmail.com> --- hw/esp.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/hw/esp.c b/hw/esp.c index 0a8cf6e..0532c67 100644 --- a/hw/esp.c +++ b/hw/esp.c @@ -423,6 +423,7 @@ static void esp_reset(DeviceState *d) { ESPState *s = container_of(d, ESPState, busdev.qdev); + esp_lower_irq(s); memset(s->rregs, 0, ESP_REGS); memset(s->wregs, 0, ESP_REGS); s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a -- 1.6.2.5