On Tue, 13 Aug 2019 10:06:58 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Aug 12, 2019 at 4:08 PM Palmer Dabbelt wrote:
On Tue, 30 Jul 2019 16:35:34 PDT (-0700), Alistair Francis wrote:
> From: Atish Patra
>
> As per the RISC-V spec, Floating Point registers are named as f0..f31
> so lets
On Mon, Aug 12, 2019 at 4:08 PM Palmer Dabbelt wrote:
>
> On Tue, 30 Jul 2019 16:35:34 PDT (-0700), Alistair Francis wrote:
> > From: Atish Patra
> >
> > As per the RISC-V spec, Floating Point registers are named as f0..f31
> > so lets fix the register names accordingly.
> >
> > Signed-off-by: At
On Tue, 30 Jul 2019 16:35:34 PDT (-0700), Alistair Francis wrote:
From: Atish Patra
As per the RISC-V spec, Floating Point registers are named as f0..f31
so lets fix the register names accordingly.
Signed-off-by: Atish Patra
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 8 ---
From: Atish Patra
As per the RISC-V spec, Floating Point registers are named as f0..f31
so lets fix the register names accordingly.
Signed-off-by: Atish Patra
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tar
