[Qemu-devel] [PATCH 0/6] tcg sparc improvements

2014-08-06 Thread Richard Henderson
Three of these patches are related to the new instructions added in 2011 with the VIS3 instruction set, as present in the T4 cpus. r~ Richard Henderson (6): tcg-sparc: Support addsub2_i64 tcg-sparc: Use ADDXC in addsub2_i64 tcg-sparc: Fix setcond_i32 uninitialized value tcg-sparc: Use

[Qemu-devel] [PATCH 0/6] tcg-sparc improvements

2010-02-16 Thread Richard Henderson
All of these patches are toward reducing the number of TCG opcodes generated. Three of the patches reduce the number of real insns generated as well. The ANDC and ORC opcodes are already generated by the ARM, PPC, and Alpha translators. I now have remote access to a real debian sparc64 machine,

[Qemu-devel] [PATCH 0/6] tcg sparc improvements

2009-12-19 Thread Richard Henderson
Here's a split up version of the patch you looked at yesterday. r~ Richard Henderson (6): tcg-sparc: Fix imm13 check in movi. tcg-sparc: Improve tcg_out_movi for sparc64. tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation. tcg: Add tcg_unsigned_cond. tcg-sparc: Implement