On 11/17/2017 10:42 AM, Mark Cave-Ayland wrote:
> Since the EBus is effectively a PCI-ISA bridge then the underlying ISA bus
> should be contained within the PCI bridge itself.
>
> Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
On Fri, Nov 17, 2017 at 4:46 PM, Mark Cave-Ayland
wrote:
> On 17/11/17 14:53, Artyom Tarasenko wrote:
>
>> On Fri, Nov 17, 2017 at 2:42 PM, Mark Cave-Ayland
>> wrote:
>>> Since the EBus is effectively a PCI-ISA bridge then the
On 17/11/17 14:53, Artyom Tarasenko wrote:
> On Fri, Nov 17, 2017 at 2:42 PM, Mark Cave-Ayland
> wrote:
>> Since the EBus is effectively a PCI-ISA bridge then the underlying ISA bus
>> should be contained within the PCI bridge itself.
>
> While it's like that on
On Fri, Nov 17, 2017 at 2:42 PM, Mark Cave-Ayland
wrote:
> Since the EBus is effectively a PCI-ISA bridge then the underlying ISA bus
> should be contained within the PCI bridge itself.
While it's like that on the Sabre chipset, the Spitfire chipset (which
I hope
Since the EBus is effectively a PCI-ISA bridge then the underlying ISA bus
should be contained within the PCI bridge itself.
Signed-off-by: Mark Cave-Ayland
---
hw/sparc64/sun4u.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git