On Sun, 10 Feb 2019 at 22:47, Richard Henderson
wrote:
>
> On 2/10/19 1:40 PM, Peter Maydell wrote:
> >> Actually, we already break the TB here by default.
> >
> > Do we? I didn't see any code (apart from the handling
> > in the DAIFSet/Clear codepaths, which aren't used for TCO).
>
> At the
On 2/10/19 1:40 PM, Peter Maydell wrote:
>> Actually, we already break the TB here by default.
>
> Do we? I didn't see any code (apart from the handling
> in the DAIFSet/Clear codepaths, which aren't used for TCO).
At the start of the function:
/* End the TB by default, chaining is ok. */
On Sun, 10 Feb 2019 at 01:23, Richard Henderson
wrote:
>
> On 2/5/19 11:27 AM, Peter Maydell wrote:
> >> +++ b/target/arm/translate-a64.c
> >> @@ -1668,6 +1668,17 @@ static void handle_msr_i(DisasContext *s, uint32_t
> >> insn,
> >> s->base.is_jmp = DISAS_UPDATE;
> >> break;
>
On 2/5/19 11:27 AM, Peter Maydell wrote:
>> +++ b/target/arm/translate-a64.c
>> @@ -1668,6 +1668,17 @@ static void handle_msr_i(DisasContext *s, uint32_t
>> insn,
>> s->base.is_jmp = DISAS_UPDATE;
>> break;
>>
>> +case 0x1c: /* TCO */
>> +if
On 2/5/19 11:27 AM, Peter Maydell wrote:
>> +#ifdef TARGET_AARCH64
>> +uint64_t tfsr_el[4]; /* tfsrel0_el1 is index 0. */
>> +uint64_t gcr_el1;
>> +uint64_t rgsr_el1;
>> +#endif
>
> Are we going to add more fields inside this #ifdef or is it only
> saving 12 words?
Just
On Mon, 14 Jan 2019 at 01:11, Richard Henderson
wrote:
>
> This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3,
> RGSR_EL1, GCR_EL1, and PSTATE.TCO.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 5 +
> target/arm/translate.h | 11 ++
>
This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3,
RGSR_EL1, GCR_EL1, and PSTATE.TCO.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
target/arm/translate.h | 11 ++
target/arm/helper.c| 45 ++
