Re: [Qemu-devel] [PATCH 06/10] ppc: Rework generation of priv and inval interrupts

2016-06-14 Thread David Gibson
On Wed, Jun 15, 2016 at 02:31:56PM +1000, Benjamin Herrenschmidt wrote: > On Wed, 2016-06-15 at 11:19 +1000, David Gibson wrote: > > > > >  static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) > > > @@ -4348,9 +4371,15 @@ static inline void gen_op_mfspr(DisasContext *ctx) > > >

Re: [Qemu-devel] [PATCH 06/10] ppc: Rework generation of priv and inval interrupts

2016-06-14 Thread Benjamin Herrenschmidt
On Wed, 2016-06-15 at 11:19 +1000, David Gibson wrote: > > >  static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) > > @@ -4348,9 +4371,15 @@ static inline void gen_op_mfspr(DisasContext *ctx) > >   TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); > >  

Re: [Qemu-devel] [PATCH 06/10] ppc: Rework generation of priv and inval interrupts

2016-06-14 Thread David Gibson
On Mon, Jun 13, 2016 at 07:24:52AM +0200, Cédric Le Goater wrote: > From: Benjamin Herrenschmidt > > Recent server processors use the Hypervisor Emulation Assistance > interrupt for illegal instructions and *some* type of SPR accesses. > > Also the code was always

[Qemu-devel] [PATCH 06/10] ppc: Rework generation of priv and inval interrupts

2016-06-12 Thread Cédric Le Goater
From: Benjamin Herrenschmidt Recent server processors use the Hypervisor Emulation Assistance interrupt for illegal instructions and *some* type of SPR accesses. Also the code was always generating inval instructions even for priv violations due to setting the wrong