Re: [Qemu-devel] [PATCH 07/10] target-avr: adding instruction decoder

2016-06-04 Thread Michael Rolnik
1. no more custings. 2. yes, it is generated code. I would like to commit the generator. however it is not very ripe yet. and it has a dependency on yaml-cpp and xsltproc. 3. the generator does not assume that same bits are extracted. it will be fixed later. 4. 0 is no longer returned. On Sun,

Re: [Qemu-devel] [PATCH 07/10] target-avr: adding instruction decoder

2016-06-04 Thread Richard Henderson
On 06/02/2016 01:06 PM, Michael Rolnik wrote: +uint32_tavr_decode(uint32_t pc, uint32_t *length, uint32_t code, translate_function_t *translate) +{ +uint32_topcode = extract32(code, 0, 16); +switch (opcode & 0xd000) { +case0x: { +uint32_t

[Qemu-devel] [PATCH 07/10] target-avr: adding instruction decoder

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik --- target-avr/decode.c | 724 1 file changed, 724 insertions(+) create mode 100644 target-avr/decode.c diff --git a/target-avr/decode.c b/target-avr/decode.c new file mode 100644 index

[Qemu-devel] [PATCH 07/10] target-avr: adding instruction decoder

2016-06-02 Thread Michael Rolnik
Signed-off-by: Michael Rolnik --- target-avr/decode.c | 724 1 file changed, 724 insertions(+) create mode 100644 target-avr/decode.c diff --git a/target-avr/decode.c b/target-avr/decode.c new file mode 100644 index