On 09/18/2018 08:47 PM, Peter Maydell wrote:
> On 31 August 2018 at 11:38, Cédric Le Goater wrote:
>> The setting of the DRAM address of the DMA transaction depends on the
>> DRAM base address and the maximun DRAM size of the SoC. Let's add a
>> couple of properties to give this information to
On 31 August 2018 at 11:38, Cédric Le Goater wrote:
> The setting of the DRAM address of the DMA transaction depends on the
> DRAM base address and the maximun DRAM size of the SoC. Let's add a
> couple of properties to give this information to the SMC controller
> model.
In hardware, does the
The setting of the DRAM address of the DMA transaction depends on the
DRAM base address and the maximun DRAM size of the SoC. Let's add a
couple of properties to give this information to the SMC controller
model.
Also, move the SDRAM Memory controller realization before the other
controllers
