On 09/18/2018 08:54 PM, Peter Maydell wrote:
> On 31 August 2018 at 11:38, Cédric Le Goater wrote:
>> When doing calibration, the SPI clock rate in the CE0 Control Register
>> and the read delay cycles in the Read Timing Compensation Register are
>> replaced by bit[11:4] of the DMA Control
On 31 August 2018 at 11:38, Cédric Le Goater wrote:
> When doing calibration, the SPI clock rate in the CE0 Control Register
> and the read delay cycles in the Read Timing Compensation Register are
> replaced by bit[11:4] of the DMA Control Register.
>
> Signed-off-by: Cédric Le Goater
> ---
>
When doing calibration, the SPI clock rate in the CE0 Control Register
and the read delay cycles in the Read Timing Compensation Register are
replaced by bit[11:4] of the DMA Control Register.
Signed-off-by: Cédric Le Goater
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hw/ssi/aspeed_smc.c | 54
