On Tue, 2016-06-21 at 07:56 +0100, Peter Maydell wrote:
> On 21 June 2016 at 04:49, Andrew Jeffery wrote:
> >
> > On Mon, 2016-06-20 at 14:57 +0100, Peter Maydell wrote:
> > >
> > > I think there are a couple of plausible ways you might model this:
> > >
> > > (a) just have a
On 21 June 2016 at 04:49, Andrew Jeffery wrote:
> On Mon, 2016-06-20 at 14:57 +0100, Peter Maydell wrote:
>> I think there are a couple of plausible ways you might model this:
>>
>> (a) just have a single property for "revision" which corresponds
>> to the revision of this bit of
On Mon, 2016-06-20 at 14:57 +0100, Peter Maydell wrote:
> On 20 June 2016 at 04:44, Andrew Jeffery wrote:
> >
> > On Fri, 2016-06-17 at 15:22 +0100, Peter Maydell wrote:
> > >
> > > +static Property aspeed_scu_properties[] = {
> > > +DEFINE_PROP_ARRAY("reset",
On 20 June 2016 at 04:44, Andrew Jeffery wrote:
> On Fri, 2016-06-17 at 15:22 +0100, Peter Maydell wrote:
>> +static Property aspeed_scu_properties[] = {
>> +DEFINE_PROP_ARRAY("reset", AspeedSCUState, num_resets, reset,
>> + qdev_prop_uint32, uint32_t),
On Fri, 2016-06-17 at 15:22 +0100, Peter Maydell wrote:
On 16 June 2016 at 08:48, Andrew Jeffery wrote:
The SCU is a collection of chip-level control registers that manage the
various functions supported by the AST2400. Typically the bits control
interactions with clocks,
On 16 June 2016 at 08:48, Andrew Jeffery wrote:
> The SCU is a collection of chip-level control registers that manage the
> various functions supported by the AST2400. Typically the bits control
> interactions with clocks, external hardware or reset behaviour, and we
> can largly
The SCU is a collection of chip-level control registers that manage the
various functions supported by the AST2400. Typically the bits control
interactions with clocks, external hardware or reset behaviour, and we
can largly take a hands-off approach to reads and writes.
Firmware makes heavy use