Re: [Qemu-devel] [PATCH 1/2] nvic: Handle ARMv6-M SCS reserved registers

2018-07-05 Thread Peter Maydell
On 5 July 2018 at 12:25, Julia Suvorova wrote: > Thank you for the review. I did not dare to set the ARM_FEATURE_M_MAIN, > because I was not completely sure about the v8M behavior in certain cases. > I'll update the code taking into account all the comments, and send v2. FWIW, I was working from

Re: [Qemu-devel] [PATCH 1/2] nvic: Handle ARMv6-M SCS reserved registers

2018-07-05 Thread Julia Suvorova via Qemu-devel
On 05.07.2018 13:54, Peter Maydell wrote: On 4 July 2018 at 20:58, Julia Suvorova wrote: Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. All reserved registers are RAZ/WI. Signed-off-by: Julia Suvorova --- hw/intc/armv7m_nvic.c | 69 +++

Re: [Qemu-devel] [PATCH 1/2] nvic: Handle ARMv6-M SCS reserved registers

2018-07-05 Thread Peter Maydell
On 4 July 2018 at 20:58, Julia Suvorova wrote: > Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. > All reserved registers are RAZ/WI. > > Signed-off-by: Julia Suvorova > --- > hw/intc/armv7m_nvic.c | 69 +++ > 1 file changed, 57 insertions(+),

[Qemu-devel] [PATCH 1/2] nvic: Handle ARMv6-M SCS reserved registers

2018-07-04 Thread Julia Suvorova via Qemu-devel
Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. All reserved registers are RAZ/WI. Signed-off-by: Julia Suvorova --- hw/intc/armv7m_nvic.c | 69 +++ 1 file changed, 57 insertions(+), 12 deletions(-) diff --git a/hw/intc/armv7m_nvic.c