Re: [Qemu-devel] [PATCH 1/3] sun4u: split out NPT and INT_DIS into separate CPUTimer fields

2016-01-08 Thread Peter Maydell
On 13 November 2015 at 17:54, Mark Cave-Ayland wrote: > Currently there is confusion between use of these bits for the timer and timer > compare registers (while they both have the same value, the behaviour is > different). Split into two separate CPUTimer fields so

Re: [Qemu-devel] [PATCH 1/3] sun4u: split out NPT and INT_DIS into separate CPUTimer fields

2016-01-08 Thread Mark Cave-Ayland
On 08/01/16 14:05, Peter Maydell wrote: > On 13 November 2015 at 17:54, Mark Cave-Ayland > wrote: >> Currently there is confusion between use of these bits for the timer and >> timer >> compare registers (while they both have the same value, the behaviour is >>

Re: [Qemu-devel] [PATCH 1/3] sun4u: split out NPT and INT_DIS into separate CPUTimer fields

2016-01-08 Thread Peter Maydell
On 8 January 2016 at 14:34, Mark Cave-Ayland wrote: > I'm not particularly worried about sun4u for the moment as there are > already other reasons why migration would fail, e.g. no > VMStateDescription for storing PCI interrupt state in the apb host bridge. > > Last

Re: [Qemu-devel] [PATCH 1/3] sun4u: split out NPT and INT_DIS into separate CPUTimer fields

2016-01-08 Thread Mark Cave-Ayland
On 08/01/16 14:55, Peter Maydell wrote: > On 8 January 2016 at 14:34, Mark Cave-Ayland > wrote: >> I'm not particularly worried about sun4u for the moment as there are >> already other reasons why migration would fail, e.g. no >> VMStateDescription for storing PCI

[Qemu-devel] [PATCH 1/3] sun4u: split out NPT and INT_DIS into separate CPUTimer fields

2015-11-13 Thread Mark Cave-Ayland
Currently there is confusion between use of these bits for the timer and timer compare registers (while they both have the same value, the behaviour is different). Split into two separate CPUTimer fields so we can always reference the correct value. Signed-off-by: Mark Cave-Ayland