On 6 December 2010 17:07, Peter Maydell peter.mayd...@linaro.org wrote:
(regarding my random-instruction-sequence testing tool)
(I really must get round to writing the README and sticking it
in a public git repo.)
The curious can find it here:
On Thu, Nov 11, 2010 at 06:23:55PM +, Peter Maydell wrote:
Correct the decoding of source and destination registers
for the VFP forms of the VCVT instructions which convert
between floating point and integer or fixed-point.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
On 6 December 2010 16:30, Nathan Froyd froy...@codesourcery.com wrote:
On Thu, Nov 11, 2010 at 06:23:55PM +, Peter Maydell wrote:
Correct the decoding of source and destination registers
for the VFP forms of the VCVT instructions which convert
between floating point and integer or
On Mon, Dec 06, 2010 at 04:48:25PM +, Peter Maydell wrote:
I'm not sure how well it would fit into being committed to qemu (yet):
it works as a program where you run half of it on real ARM hardware
and the other half under qemu (or valgrind) and it compares register
results after executing
On 6 December 2010 16:57, Nathan Froyd froy...@codesourcery.com wrote:
FWIW--and this is not particularly conducive to random insn
sequences--the approach taken when doing the AltiVec bits was to have
code that looked like:
for each insn:
for a suitable set of inputs:
setup
Correct the decoding of source and destination registers
for the VFP forms of the VCVT instructions which convert
between floating point and integer or fixed-point.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/translate.c | 19 ---
1 files changed, 12
