Hi Paolo,
There's a fork that has linux-user support. We'll get it added into the
downstream riscv-qemu repo and include that in the next patch set instead
of softmmu.
Thanks,
Sagar
On Mon, Sep 26, 2016 at 5:44 AM, Paolo Bonzini wrote:
>
>
> On 26/09/2016 14:38, Bastian
On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
+void helper_fence_i(CPURISCVState *env)
+{
+RISCVCPU *cpu = riscv_env_get_cpu(env);
+CPUState *cs = CPU(cpu);
+/* Flush QEMU's TLB */
+tlb_flush(cs, 1);
+/* ARM port seems to not know if this is okay inside a TB
+ But we
On 26/09/2016 14:38, Bastian Koppelmann wrote:
> On 09/26/2016 02:21 PM, Paolo Bonzini wrote:
>>
>>
>> On 26/09/2016 12:56, Sagar Karandikar wrote:
>>> +#ifndef CONFIG_USER_ONLY
>>> +DEF_HELPER_4(csrrw, tl, env, tl, tl, tl)
>>> +DEF_HELPER_5(csrrs, tl, env, tl, tl, tl, tl)
>>>
On 09/26/2016 02:21 PM, Paolo Bonzini wrote:
>
>
> On 26/09/2016 12:56, Sagar Karandikar wrote:
>> +#ifndef CONFIG_USER_ONLY
>> +DEF_HELPER_4(csrrw, tl, env, tl, tl, tl)
>> +DEF_HELPER_5(csrrs, tl, env, tl, tl, tl, tl)
>> +DEF_HELPER_5(csrrc, tl, env, tl, tl, tl, tl)
>> +DEF_HELPER_2(sret, tl,
On 26/09/2016 12:56, Sagar Karandikar wrote:
> +#ifndef CONFIG_USER_ONLY
> +DEF_HELPER_4(csrrw, tl, env, tl, tl, tl)
> +DEF_HELPER_5(csrrs, tl, env, tl, tl, tl, tl)
> +DEF_HELPER_5(csrrc, tl, env, tl, tl, tl, tl)
> +DEF_HELPER_2(sret, tl, env, tl)
> +DEF_HELPER_2(mret, tl, env, tl)
>
System instructions, stubs for csr read/write, necessary helpers
Signed-off-by: Sagar Karandikar
---
target-riscv/helper.h| 11
target-riscv/op_helper.c | 144 +++
target-riscv/translate.c | 119