PAPR defines an interrupt control architecture which is logically divided
into ICS (Interrupt Control Presentation, each unit is responsible for
presenting interrupts to a particular interrupt server, i.e. CPU) and
ICS (Interrupt Control Source, each unit responsible for one or more
hardware
PAPR defines an interrupt control architecture which is logically divided
into ICS (Interrupt Control Presentation, each unit is responsible for
presenting interrupts to a particular interrupt server, i.e. CPU) and
ICS (Interrupt Control Source, each unit responsible for one or more
hardware
PAPR defines an interrupt control architecture which is logically divided
into ICS (Interrupt Control Presentation, each unit is responsible for
presenting interrupts to a particular interrupt server, i.e. CPU) and
ICS (Interrupt Control Source, each unit responsible for one or more
hardware