[Qemu-devel] [PATCH 18/27] Implement the PAPR (pSeries) virtualized interrupt controller (xics)

2011-03-31 Thread David Gibson
PAPR defines an interrupt control architecture which is logically divided into ICS (Interrupt Control Presentation, each unit is responsible for presenting interrupts to a particular interrupt server, i.e. CPU) and ICS (Interrupt Control Source, each unit responsible for one or more hardware

[Qemu-devel] [PATCH 18/27] Implement the PAPR (pSeries) virtualized interrupt controller (xics)

2011-03-24 Thread David Gibson
PAPR defines an interrupt control architecture which is logically divided into ICS (Interrupt Control Presentation, each unit is responsible for presenting interrupts to a particular interrupt server, i.e. CPU) and ICS (Interrupt Control Source, each unit responsible for one or more hardware

[Qemu-devel] [PATCH 18/27] Implement the PAPR (pSeries) virtualized interrupt controller (xics)

2011-03-22 Thread David Gibson
PAPR defines an interrupt control architecture which is logically divided into ICS (Interrupt Control Presentation, each unit is responsible for presenting interrupts to a particular interrupt server, i.e. CPU) and ICS (Interrupt Control Source, each unit responsible for one or more hardware