Re: [Qemu-devel] [PATCH 2/2] target/riscv: Add checks for several RVC reserved operands

2019-05-01 Thread Palmer Dabbelt
On Thu, 25 Apr 2019 10:32:43 PDT (-0700), richard.hender...@linaro.org wrote: On 4/25/19 10:26 AM, Richard Henderson wrote: { + illegal 011 0 - 0 01 # c.addi16sp, RES nzimm=0 addi011 . 00010 . 01 @c_addi16sp lui 011 . . . 01

Re: [Qemu-devel] [PATCH 2/2] target/riscv: Add checks for several RVC reserved operands

2019-04-25 Thread Richard Henderson
On 4/25/19 10:26 AM, Richard Henderson wrote: > { > + illegal 011 0 - 0 01 # c.addi16sp, RES nzimm=0 >addi011 . 00010 . 01 @c_addi16sp >lui 011 . . . 01 @c_lui > } Bah. I just realized the comment should be more like #

[Qemu-devel] [PATCH 2/2] target/riscv: Add checks for several RVC reserved operands

2019-04-25 Thread Richard Henderson
C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Signed-off-by: Richard Henderson --- target/riscv/insn16-64.decode | 10 -- target/riscv/insn16.decode| 7 ++- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git