Hello, Leon, thank you very much for the kind feedback. Let me clarify my take
on the involved issues.
1) Class operations
I am going to correct the code as you hinted.
The reason I wanted separate handling of MSA class operation is code and module
decoupling. Handling of MSA instructions (in
On 25/03/16 12:50, Aleksandar Markovic wrote:
> +#define MSA_CLASS_SIGNALING_NAN 0x001
> +#define MSA_CLASS_QUIET_NAN 0x002
> +#define MSA_CLASS_NEGATIVE_INFINITY 0x004
> +#define MSA_CLASS_NEGATIVE_NORMAL0x008
> +#define MSA_CLASS_NEGATIVE_SUBNORMAL 0x010
> +#define MSA_CLASS_NE
On 03/31/2016 04:55 AM, Aleksandar Markovic wrote:
> Hi, Richard, what would you think about this approach:
>
> Functionality of . and ..
> instructions is dependent on flags ABS2008 and NAN2008 in FCR31. There are
> MIPS architectures (for example mips32r5) that allow implementations
> with diffe
jcmvb...@gmail.com; Miodrag Dinic;
qemu-...@nongnu.org; qemu-...@nongnu.org; edgar.igles...@gmail.com;
pbonz...@redhat.com; g...@mprc.pku.edu.cn; Leon Alrae; afaer...@suse.de;
aurel...@aurel32.net; pro...@gmail.com
Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: Implement IEEE 754-2008
fu
: [Qemu-devel] [PATCH 2/2] target-mips: Implement IEEE 754-2008
functionality for R6 and MSA instructions
On 03/25/2016 05:50 AM, Aleksandar Markovic wrote:
> @@ -2621,9 +2621,23 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env,
> uint64_t fdt0)
> uint64_t dt2;
>
> dt2 = f
On 03/25/2016 05:50 AM, Aleksandar Markovic wrote:
@@ -2621,9 +2621,23 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t
fdt0)
uint64_t dt2;
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
-if (get_float_exception_flags(&env->active_fpu.fp_status)
-&
From: Aleksandar Markovic
This patch utilizes provisions from the previous patch, and configures
Mips R6 CPUs and Mips MSA units appropriately with reference to the meaning
of the signaling NaN bit (this is mentioned in point 3 in the list below).
The majority of involved MIPS instructions will b
