Note: The series is incomplete, for review only PCI spec requires that a transaction that has not been claimed by any PCI bus devices will be terminated by the initiator with "master abort". For read transactions -1(FFFFFFFF) is returned and writes are silently dropped.
The series deals also with the other aspect of the master abort scenario: Upon completion the master has to raise RECEIVED MASTER ABORT BIT in initiator's STATUS register. Implementation: - Allowed the MemoryRegion priority to be negative so a subregion will be visible on all the addresses not covered by the parent MemoryRegion or other subregions. - Added a memory region with negative priority that extends over all the pci address space. This region catches all the accesses to the unassigned pci addresses. - The MemoryRegion's ops emulates the master abort scenario. Note: For the moment the code assumes that all the reads/writes to pci address space are done by the cpu. Changes from v1: - "pci-unassigned-mem" MemoryRegion resides now in PCIBus and not on various Host Bridges - "pci-unassgined-mem" does not have a ".valid.accept" field and implements read write methods Marcel Apfelbaum (3): memory: allow MemoryRegion's priority field to accept negative values hw/pci: add MemoryRegion ops for unassigned pci addresses hw/pci-host: catch acesses to unassigned pci addresses hw/pci-host/piix.c | 8 ++++++++ hw/pci-host/q35.c | 19 ++++++++++++++++--- hw/pci/pci.c | 18 ++++++++++++++++++ include/exec/memory.h | 6 +++--- include/hw/pci-host/q35.h | 1 + include/hw/pci/pci.h | 3 +++ memory.c | 2 +- 7 files changed, 50 insertions(+), 7 deletions(-) -- 1.8.3.1