Re: [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU

2019-04-09 Thread Alistair Francis
On Thu, Apr 4, 2019 at 5:35 AM Ian Campbell wrote: > > On Fri, 2019-03-29 at 22:39 +, Alistair Francis wrote: > > +for (i = 0; i < strlen(riscv_cpu); i++) { > > +if (i == 0 && riscv_cpu[i] == 'r' && > > +riscv_cpu[i + 1] == 'v') { > > Dpes something somewhere else

Re: [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU

2019-04-04 Thread Ian Campbell
On Fri, 2019-03-29 at 22:39 +, Alistair Francis wrote: > +for (i = 0; i < strlen(riscv_cpu); i++) { > +if (i == 0 && riscv_cpu[i] == 'r' && > +riscv_cpu[i + 1] == 'v') { Dpes something somewhere else enforce a minimum length or can `riscv_cpu[i + 1]` be past the end of

[Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU

2019-03-29 Thread Alistair Francis
If a user specifies a CPU that we don't understand then we want to fall back to a CPU generated from the ISA string. At the moment the generated CPU is assumed to be a privledge spec version 1.10 CPU with an MMU. This can be changed in the future. Signed-off-by: Alistair Francis ---