On 09/09/2015 14:03, Ефимов Василий wrote:
> We also can set up redirection at machine initialization, but using of
> listener makes sure redirection is actual at runtime. I do not know
> case in which regions at the PAM addresses are changed dynamically
> during guest work. But even during
07.09.2015 15:50, Paolo Bonzini пишет:
Hi Vasily,
I agree that this patch is an improvement compared to the earlier
versions, but it's still a bit of an abstraction violation and I'm not
sure if it works with KVM.
It does not work with KVM. BIOS freezes on 0xCAA26 on
mov %ax,%es
instruction
Ping
Vasily
On 20/07/2015 12:53, Efimov Vasily wrote:
> +read_src = address_space_translate(read_as, pam_offset,
> + _within_read_leaf, ,
> + false);
> +
> +if (memory_region_is_ram(read_src) ||
22.07.2015 19:37, Kevin O'Connor пишет:
Hi,
Hi,
Is the motivation of this patch to improve the correctness of the
hardware emulation or is there some feature that the current QEMU
implementation prevents?
The motivation is to improve correctness. The current QEMU PAM
implementation prevents
On Mon, Jul 20, 2015 at 01:53:13PM +0300, Efimov Vasily wrote:
This patch improves PAM emulation.
PAM defines 4 memory access redirection modes. In mode 1 reads are directed to
RAM and writes are directed to PCI. In mode 2 it is contrary. In mode 0 all
access is directed to PCI. In mode 3 it
On 20/07/2015 12:53, Efimov Vasily wrote:
This patch improves PAM emulation.
PAM defines 4 memory access redirection modes. In mode 1 reads are directed to
RAM and writes are directed to PCI. In mode 2 it is contrary. In mode 0 all
access is directed to PCI. In mode 3 it is directed to
21.07.2015 10:46, Paolo Bonzini пишет:
Out of curiosity, would it be necessary to flush the TLB when the PAM
registers change?
In QEMU, the TLB also has the function of a cache in some sense
(because, by pointing to a ram_addr_t, it prevents reads, writes or
fetches from going through the slow
This patch improves PAM emulation.
PAM defines 4 memory access redirection modes. In mode 1 reads are directed to
RAM and writes are directed to PCI. In mode 2 it is contrary. In mode 0 all
access is directed to PCI. In mode 3 it is directed to RAM. Currently all modes
are emulated using aliases.
