Re: [Qemu-devel] [PATCH v2] hw/intc/arm_gic.c: Implement GICv2 GICC_DIR

2016-03-01 Thread Peter Maydell
On 1 March 2016 at 19:58, Sergey Fedorov wrote: > On 01.03.2016 20:42, Peter Maydell wrote: >> >> The GICv2 introduces a new CPU interface register GICC_DIR, which >> allows an OS to split the "priority drop" and "deactivate interrupt" >> parts of interrupt completion.

Re: [Qemu-devel] [PATCH v2] hw/intc/arm_gic.c: Implement GICv2 GICC_DIR

2016-03-01 Thread Sergey Fedorov
On 01.03.2016 20:42, Peter Maydell wrote: The GICv2 introduces a new CPU interface register GICC_DIR, which allows an OS to split the "priority drop" and "deactivate interrupt" parts of interrupt completion. Implement this register. (Note that the register is at offset 0x1000 in the CPU

[Qemu-devel] [PATCH v2] hw/intc/arm_gic.c: Implement GICv2 GICC_DIR

2016-03-01 Thread Peter Maydell
The GICv2 introduces a new CPU interface register GICC_DIR, which allows an OS to split the "priority drop" and "deactivate interrupt" parts of interrupt completion. Implement this register. (Note that the register is at offset 0x1000 in the CPU interface, which means it is on a different 4K page