On 9/14/19 10:58 AM, Richard Henderson wrote:
> On 9/12/19 8:54 AM, Paul A. Clarke wrote:
>> +static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1)
>> +{
>> +TCGv_i64 t0 = tcg_temp_new_i64();
>> +TCGv_i32 mask = tcg_const_i32(0x0001);
>> +
>> +gen_reset_fpstatus();
>> +tcg_
On 9/12/19 8:54 AM, Paul A. Clarke wrote:
> +static void gen_helper_mffscrn(DisasContext *ctx, TCGv_i64 t1)
> +{
> +TCGv_i64 t0 = tcg_temp_new_i64();
> +TCGv_i32 mask = tcg_const_i32(0x0001);
> +
> +gen_reset_fpstatus();
> +tcg_gen_extu_tl_i64(t0, cpu_fpscr);
> +tcg_gen_andi_i64
From: "Paul A. Clarke"
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffscrn' and 'mffscrni' instructions.
'mffscrn' and 'mffscrni' are similar to 'mffsl', except they d
