On Thu, 05 Sep 2019 08:57:44 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Thu, Sep 5, 2019 at 11:55 PM Bin Meng wrote:
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
---
Changes in
Hi Palmer,
On Thu, Sep 5, 2019 at 11:55 PM Bin Meng wrote:
>
> This adds a reset opcode for sifive_test device to trigger a system
> reset for testing purpose.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Palmer Dabbelt
>
> ---
>
> Changes in v2:
> - fix build error in the "for-master" branch of
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
---
Changes in v2:
- fix build error in the "for-master" branch of Palmer's RISC-V repo
that was rebased on QEMU master
hw/riscv/sifive_test.c
