On 09 Jun 2014, at 17:18, Peter Maydell peter.mayd...@linaro.org wrote:
On 9 June 2014 12:27, Peter Maydell peter.mayd...@linaro.org wrote:
On 5 June 2014 11:39, Fabian Aggeler aggel...@ethz.ch wrote:
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).
Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
get_level1_table_address.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
v2 -
Obviously not v2 but v3 (subject). Sorry for that, please ignore it as I am
going to resend.
Regards,
Fabian
On 10 Jun 2014, at 16:12, Fabian Aggeler aggel...@ethz.ch wrote:
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1
On 10 June 2014 18:00, Aggeler Fabian aggel...@student.ethz.ch wrote:
Obviously not v2 but v3 (subject). Sorry for that, please ignore it as I am
going to resend.
You don't need to resend just for that. Applied to target-arm.next.
thanks
-- PMM
On 5 June 2014 11:39, Fabian Aggeler aggel...@ethz.ch wrote:
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).
Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
On 9 June 2014 12:27, Peter Maydell peter.mayd...@linaro.org wrote:
On 5 June 2014 11:39, Fabian Aggeler aggel...@ethz.ch wrote:
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).
Bits
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).
Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
get_level1_table_address.
Signed-off-by: Fabian Aggeler aggel...@ethz.ch
---
v1 -
Reviewed by: Greg Bellows greg.bell...@linaro.org
On 5 June 2014 05:39, Fabian Aggeler aggel...@ethz.ch wrote:
Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).
Bits PD0/PD1 are now
