Re: [Qemu-devel] [PATCH v2 03/17] RISC-V: support vector extension csr

2019-09-14 Thread Palmer Dabbelt
On Wed, 11 Sep 2019 15:43:29 PDT (-0700), richard.hender...@linaro.org wrote: On 9/11/19 2:25 AM, liuzhiwei wrote: @@ -873,7 +925,12 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, [CSR_FRM] =

Re: [Qemu-devel] [PATCH v2 03/17] RISC-V: support vector extension csr

2019-09-11 Thread Richard Henderson
On 9/11/19 2:25 AM, liuzhiwei wrote: > @@ -873,7 +925,12 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_FFLAGS] = { fs, read_fflags, write_fflags > }, > [CSR_FRM] = { fs, read_frm, write_frm > }, >

[Qemu-devel] [PATCH v2 03/17] RISC-V: support vector extension csr

2019-09-11 Thread liuzhiwei
From: LIU Zhiwei Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 15 target/riscv/csr.c | 65 ++--- 2 files changed, 76 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index