Re: [Qemu-devel] [PATCH v2 04/17] RISC-V: add vector extension configure instruction

> +void VECTOR_HELPER(vsetvl)(CPURISCVState *env, uint32_t rs1, uint32_t rs2, > +uint32_t rd) > +{ > +int sew, max_sew, vlmax, vl; > + > +if (rs2 == 0) { > +vector_vtype_set_ill(env); > +riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > +return; >

[Qemu-devel] [PATCH v2 04/17] RISC-V: add vector extension configure instruction

From: LIU Zhiwei Signed-off-by: LIU Zhiwei --- target/riscv/Makefile.objs | 2 +- target/riscv/helper.h | 3 + target/riscv/insn32.decode | 5 ++ target/riscv/insn_trans/trans_rvv.inc.c | 46 target/riscv/translate.c