Re: [Qemu-devel] [PATCH v2 08/17] RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc

2019-09-12 Thread Richard Henderson
On 9/12/19 11:27 AM, Richard Henderson wrote: >> +void VECTOR_HELPER(vadc_vxm)(CPURISCVState *env, uint32_t rs1, >> +uint32_t rs2, uint32_t rd) >> +{ > > Watch the spacing between functions. > Pass gpr rs1 by value. > >> +void VECTOR_HELPER(vadc_vim)(CPURISCVState *env, uint32_t rs1, >> +

Re: [Qemu-devel] [PATCH v2 08/17] RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc

2019-09-12 Thread Richard Henderson
On 9/11/19 2:25 AM, liuzhiwei wrote: > #define VECTOR_HELPER(name) HELPER(glue(vector_, name)) > +#define SIGNBIT8(1 << 7) > +#define SIGNBIT16 (1 << 15) > +#define SIGNBIT32 (1 << 31) > +#define SIGNBIT64 ((uint64_t)1 << 63) Perhaps make up your mind if you want signed or unsigned valu

[Qemu-devel] [PATCH v2 08/17] RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc

2019-09-10 Thread liuzhiwei
From: LIU Zhiwei Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 36 + target/riscv/insn32.decode | 35 + target/riscv/insn_trans/trans_rvv.inc.c | 49 + target/riscv/vector_helper.c| 2335 +++ 4 files changed, 2