Re: [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions

2018-10-08 Thread Aleksandar Markovic
> From: Dimitrije Nikolic > > Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE, LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE. > > Signed-off-by: Aleksandar Markovic This patch is incomplete. The pool P.LS.E0 has three subpools, and, for each of them,

Re: [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions

2018-10-05 Thread Philippe Mathieu-Daudé
On 05/10/2018 17:19, Aleksandar Markovic wrote: > From: Dimitrije Nikolic > > Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE, > LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE. B.44 of "nanoMIPS32 Instruction Set Technical Reference Manual" > Signed-off-by:

[Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions

2018-10-05 Thread Aleksandar Markovic
From: Dimitrije Nikolic Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE, LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 16 1 file changed, 16 insertions(+) diff --git