On Tue, Jan 7, 2020 at 10:21 PM Alex Bennée wrote:
>
>
> Georg Kotheimer writes:
>
> > The size of the FPU registers depends solely on the floating point
> > extensions supported by the target architecture.
> > However, in the previous implementation the floating point register
> > size was
Georg Kotheimer writes:
> The size of the FPU registers depends solely on the floating point
> extensions supported by the target architecture.
> However, in the previous implementation the floating point register
> size was derived from whether the target architecture is 32-bit or
> 64-bit.
>
On Wed, Aug 21, 2019 at 9:36 AM Georg Kotheimer
wrote:
>
> The size of the FPU registers depends solely on the floating point
> extensions supported by the target architecture.
> However, in the previous implementation the floating point register
> size was derived from whether the target
On 8/21/19 9:28 AM, Georg Kotheimer wrote:
The size of the FPU registers depends solely on the floating point
extensions supported by the target architecture.
However, in the previous implementation the floating point register
size was derived from whether the target architecture is 32-bit or
The size of the FPU registers depends solely on the floating point
extensions supported by the target architecture.
However, in the previous implementation the floating point register
size was derived from whether the target architecture is 32-bit or
64-bit.
To allow RVF without RVD, changes to
