Re: [Qemu-devel] [PATCH v3] arm: implement cache/shareability attribute bits for PAR registers

2017-10-31 Thread Peter Maydell
On 31 October 2017 at 13:02, Andrew Baumann wrote: > On a successful address translation instruction, PAR is supposed to > contain cacheability and shareability attributes determined by the > translation. We previously returned 0 for these bits (in line with the >

Re: [Qemu-devel] [PATCH v3] arm: implement cache/shareability attribute bits for PAR registers

2017-10-31 Thread Andrew Baumann via Qemu-devel
> From: Andrew Baumann > Sent: Tuesday, 31 October 2017 21:02 [...] > +static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) > +{ > +uint8_t hiattr = extract32(s2attrs, 2, 2); > +uint8_t loattr = extract32(s2attrs, 0, 2); > +uint8_t hihint = 0, lohint = 0; > + > +

[Qemu-devel] [PATCH v3] arm: implement cache/shareability attribute bits for PAR registers

2017-10-31 Thread Andrew Baumann via Qemu-devel
On a successful address translation instruction, PAR is supposed to contain cacheability and shareability attributes determined by the translation. We previously returned 0 for these bits (in line with the general strategy of ignoring caches and memory attributes), but some guest OSes may depend