I believe I've incorporated all of Peter's feedback from v2. This is based on target-arm.next, which now contains Alex's fp16 work.
Re-tested our standard aarch64 risu tests with -cpu cortex-a57, and against the new risu tests I posted this morning for aa64 and aa32. r~ Richard Henderson (16): target/arm: Add ARM_FEATURE_V8_RDM target/arm: Refactor disas_simd_indexed decode target/arm: Refactor disas_simd_indexed size checks target/arm: Decode aa64 armv8.1 scalar three same extra target/arm: Decode aa64 armv8.1 three same extra target/arm: Decode aa64 armv8.1 scalar/vector x indexed element target/arm: Decode aa32 armv8.1 three same target/arm: Decode aa32 armv8.1 two reg and a scalar target/arm: Enable ARM_FEATURE_V8_RDM target/arm: Add ARM_FEATURE_V8_FCMA target/arm: Decode aa64 armv8.3 fcadd target/arm: Decode aa64 armv8.3 fcmla target/arm: Decode aa32 armv8.3 3-same target/arm: Decode aa32 armv8.3 2-reg-index target/arm: Decode t32 simd 3reg and 2reg_scalar extension target/arm: Enable ARM_FEATURE_V8_FCMA target/arm/cpu.h | 2 + target/arm/helper.h | 31 +++ linux-user/elfload.c | 2 + target/arm/cpu.c | 2 + target/arm/cpu64.c | 2 + target/arm/translate-a64.c | 514 ++++++++++++++++++++++++++++++++++++--------- target/arm/translate.c | 275 +++++++++++++++++++++--- target/arm/vec_helper.c | 429 +++++++++++++++++++++++++++++++++++++ target/arm/Makefile.objs | 2 +- 9 files changed, 1133 insertions(+), 126 deletions(-) create mode 100644 target/arm/vec_helper.c -- 2.14.3