Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-27 Thread David Gibson
On Tue, Sep 27, 2016 at 07:54:37AM +0200, Cédric Le Goater wrote: > On 09/27/2016 04:35 AM, David Gibson wrote: > > On Mon, Sep 26, 2016 at 06:11:36PM +0200, Cédric Le Goater wrote: > >> On 09/23/2016 04:46 AM, David Gibson wrote: > >>> On Thu, Sep 22, 2016 at 10:25:59AM +0200, Cédric Le Goater

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-27 Thread Benjamin Herrenschmidt
On Tue, 2016-09-27 at 11:10 +0200, Cédric Le Goater wrote: > >  > > > > > > +PowerPCCPU *cpu = POWERPC_CPU(cs); > > > +CPUPPCState *env = >env; > > > + > > > +cpu_synchronize_state(cs); > > > +env->spr[SPR_HMER] |= hmer_bits; > > > + > > > +/* XXX Need a CPU helper to set

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-27 Thread Benjamin Herrenschmidt
On Tue, 2016-09-27 at 11:30 +0200, Cédric Le Goater wrote: > On 09/27/2016 11:10 AM, Cédric Le Goater wrote: > > > > > > > > > > > > > +#include > > > > + > > > > +static void xscom_complete(uint64_t hmer_bits) > > > > +{ > > > > +CPUState *cs = current_cpu; > > > > > > Hmm.. is

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-27 Thread Cédric Le Goater
On 09/27/2016 11:10 AM, Cédric Le Goater wrote: >>> +#include >>> + >>> +static void xscom_complete(uint64_t hmer_bits) >>> +{ >>> +CPUState *cs = current_cpu; >> >> Hmm.. is current_cpu a safe thing to use in the case of KVM or MTTCG? > > yes, as we are running under cpu_exec when doing

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-27 Thread Cédric Le Goater
>> +#include >> + >> +static void xscom_complete(uint64_t hmer_bits) >> +{ >> +CPUState *cs = current_cpu; > > Hmm.. is current_cpu a safe thing to use in the case of KVM or MTTCG? yes, as we are running under cpu_exec when doing this call. >> +PowerPCCPU *cpu = POWERPC_CPU(cs); >> +

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-27 Thread Cédric Le Goater
On 09/27/2016 08:10 AM, Benjamin Herrenschmidt wrote: > On Tue, 2016-09-27 at 07:54 +0200, Cédric Le Goater wrote: >> >>> but I guess if you have the decoding of those "core" registers >>> here as well, then that doesn't make so much sense. > > Those core registers may well change with P9, we

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-27 Thread Benjamin Herrenschmidt
On Tue, 2016-09-27 at 07:54 +0200, Cédric Le Goater wrote: > > > but I guess if you have the decoding of those "core" registers  > > here as well, then that doesn't make so much sense. Those core registers may well change with P9, we havne't looked closely yet... > yes and there is also the

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-26 Thread Cédric Le Goater
On 09/27/2016 04:35 AM, David Gibson wrote: > On Mon, Sep 26, 2016 at 06:11:36PM +0200, Cédric Le Goater wrote: >> On 09/23/2016 04:46 AM, David Gibson wrote: >>> On Thu, Sep 22, 2016 at 10:25:59AM +0200, Cédric Le Goater wrote: >> @@ -493,6 +525,8 @@ static void

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-26 Thread David Gibson
On Mon, Sep 26, 2016 at 06:11:36PM +0200, Cédric Le Goater wrote: > On 09/23/2016 04:46 AM, David Gibson wrote: > > On Thu, Sep 22, 2016 at 10:25:59AM +0200, Cédric Le Goater wrote: > @@ -493,6 +525,8 @@ static void pnv_chip_power9_class_init(ObjectClass > *klass, void *data) >

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-26 Thread Cédric Le Goater
On 09/23/2016 04:46 AM, David Gibson wrote: > On Thu, Sep 22, 2016 at 10:25:59AM +0200, Cédric Le Goater wrote: @@ -493,6 +525,8 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) k->chip_cfam_id = 0x100d10498000ull; /* P9 Nimbus DD1.0 */

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-22 Thread David Gibson
On Thu, Sep 22, 2016 at 10:25:59AM +0200, Cédric Le Goater wrote: > >> @@ -493,6 +525,8 @@ static void pnv_chip_power9_class_init(ObjectClass > >> *klass, void *data) > >> k->chip_cfam_id = 0x100d10498000ull; /* P9 Nimbus DD1.0 */ > >> k->cores_mask = POWER9_CORE_MASK; > >>

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-22 Thread Cédric Le Goater
>> @@ -493,6 +525,8 @@ static void pnv_chip_power9_class_init(ObjectClass >> *klass, void *data) >> k->chip_cfam_id = 0x100d10498000ull; /* P9 Nimbus DD1.0 */ >> k->cores_mask = POWER9_CORE_MASK; >> k->core_pir = pnv_chip_core_pir_p9; >> +k->xscom_addr =

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-21 Thread Benjamin Herrenschmidt
On Wed, 2016-09-21 at 15:56 +1000, David Gibson wrote: > > Yes, I think that's the way to go. > > That also means on P9 you can potentially just map the scom address > space directly into address_space_memory, instead of requiring a > redispatcher to do the address mangling. No. You still need

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-21 Thread David Gibson
On Thu, Sep 15, 2016 at 02:45:57PM +0200, Cédric Le Goater wrote: > On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves > as a backbone to connect different units of the system. The host > firmware connects to the PIB through a bridge unit, the > Alter-Display-Unit (ADU), which

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-21 Thread David Gibson
On Fri, Sep 16, 2016 at 08:11:45AM +1000, Benjamin Herrenschmidt wrote: > On Thu, 2016-09-15 at 14:45 +0200, Cédric Le Goater wrote: > >  - The PCB translation is too much of a constraint for a specific > >    XSCOM address space, unless someone can explain me how to address 8 > >    bytes at

Re: [Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-15 Thread Benjamin Herrenschmidt
On Thu, 2016-09-15 at 14:45 +0200, Cédric Le Goater wrote: >  - The PCB translation is too much of a constraint for a specific >    XSCOM address space, unless someone can explain me how to address 8 >    bytes at 0xb0021 and another 8 different bytes at 0xb0022. I don't >    think the address

[Qemu-devel] [PATCH v3 07/10] ppc/pnv: add XSCOM infrastructure

2016-09-15 Thread Cédric Le Goater
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves as a backbone to connect different units of the system. The host firmware connects to the PIB through a bridge unit, the Alter-Display-Unit (ADU), which gives him access to all the chiplets on the PCB network (Pervasive Connect