Re: [Qemu-devel] [PATCH v3 1/2] intel_iommu: check validity for GAW bits in CE

> From: Peter Xu [mailto:pet...@redhat.com] > Sent: Wednesday, December 14, 2016 10:54 AM > > On Wed, Dec 14, 2016 at 04:48:42AM +0200, Michael S. Tsirkin wrote: > > On Wed, Dec 14, 2016 at 10:09:04AM +0800, Peter Xu wrote: > > > Currently vt-d Context Entry (CE) only allows 39/48 bits address

Re: [Qemu-devel] [PATCH v3 1/2] intel_iommu: check validity for GAW bits in CE

On Wed, Dec 14, 2016 at 04:48:42AM +0200, Michael S. Tsirkin wrote: > On Wed, Dec 14, 2016 at 10:09:04AM +0800, Peter Xu wrote: > > Currently vt-d Context Entry (CE) only allows 39/48 bits address width. > > If guest software configured more than that, we complain and report. > > > >

Re: [Qemu-devel] [PATCH v3 1/2] intel_iommu: check validity for GAW bits in CE

On Wed, Dec 14, 2016 at 10:09:04AM +0800, Peter Xu wrote: > Currently vt-d Context Entry (CE) only allows 39/48 bits address width. > If guest software configured more than that, we complain and report. > > Signed-off-by: Peter Xu > --- > hw/i386/intel_iommu.c | 17

[Qemu-devel] [PATCH v3 1/2] intel_iommu: check validity for GAW bits in CE

Currently vt-d Context Entry (CE) only allows 39/48 bits address width. If guest software configured more than that, we complain and report. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 17 - hw/i386/intel_iommu_internal.h | 2 ++ 2 files