Re: [Qemu-devel] [PATCH v3 2/2] ppc: Add support for 'mffsce' instruction

2019-09-18 Thread David Gibson
On Wed, Sep 18, 2019 at 09:31:22AM -0500, Paul A. Clarke wrote: > From: "Paul A. Clarke" > > ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) > instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. > This patch adds support for 'mffsce' instruction. > > '

[Qemu-devel] [PATCH v3 2/2] ppc: Add support for 'mffsce' instruction

2019-09-18 Thread Paul A. Clarke
From: "Paul A. Clarke" ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. This patch adds support for 'mffsce' instruction. 'mffsce' is identical to 'mffs', except that it also clears the exception enabl