On 1/11/19 10:00 PM, Richard Henderson wrote:
On 1/12/19 12:10 AM, Bastian Koppelmann wrote:
On 10/31/18 11:18 PM, Richard Henderson wrote:
Surely the shri and sari functions need the same shamt >= TARGET_LONG_BITS
check as slli. Otherwise RV32 shri should definitely produce an assert in
On 1/12/19 12:10 AM, Bastian Koppelmann wrote:
>
> On 10/31/18 11:18 PM, Richard Henderson wrote:
>>
>> Surely the shri and sari functions need the same shamt >= TARGET_LONG_BITS
>> check as slli. Otherwise RV32 shri should definitely produce an assert in
>> tcg_gen_shri_tl.
>>
>> I did wonder
On 10/31/18 11:18 PM, Richard Henderson wrote:
Surely the shri and sari functions need the same shamt >= TARGET_LONG_BITS
check as slli. Otherwise RV32 shri should definitely produce an assert in
tcg_gen_shri_tl.
I did wonder about changing the decode of the shift functions such that only
On 10/31/18 1:20 PM, Bastian Koppelmann wrote:
> +
> +#ifdef TARGET_RISCV64
> +static void gen_addiw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +tcg_gen_add_tl(ret, arg1, arg2);
> +tcg_gen_ext32s_tl(ret, ret);
> +}
> +#endif
This should have been called gen_addw. It takes no immediate.
r~
On 10/31/18 1:20 PM, Bastian Koppelmann wrote:
> static bool trans_slli(DisasContext *ctx, arg_slli *a)
> {
> -gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
> +if (a->rd != 0) {
> +TCGv t = tcg_temp_new();
> +gen_get_gpr(t, a->rs1);
> +
> +if
gen_arith_imm() does a lot of decoding manually, which was hard to read
in
case of the shift instructions and is not necessary anymore with
decodetree.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v2 -> v3:
- trans_srli/srai now use tcg_gen_shri/srai_tl
- trans_addiw
