Re: [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong

2019-08-23 Thread Alistair Francis
On Thu, Aug 15, 2019 at 2:38 PM Alistair Francis wrote: > > The mip register is an MXLEN-bit long register. Convert it to a > target_ulong type instead of uint32_t. > > Signed-off-by: Alistair Francis MIP is 32-bit to allow atomic access on 32-bit hosts, so I am going to send a v4 with this

Re: [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong

2019-08-16 Thread Bin Meng
On Fri, Aug 16, 2019 at 5:44 AM Alistair Francis wrote: > > The mip register is an MXLEN-bit long register. Convert it to a > target_ulong type instead of uint32_t. > > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >

[Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong

2019-08-15 Thread Alistair Francis
The mip register is an MXLEN-bit long register. Convert it to a target_ulong type instead of uint32_t. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2dc9b17678..0a7985c3f7