Re: [Qemu-devel] [PATCH v4] aspeed_scu: Implement RNG register

2018-06-15 Thread Peter Maydell
On 13 June 2018 at 12:48, Joel Stanley wrote: > The ASPEED SoCs contain a single register that returns random data when > read. This models that register so that guests can use it. > > The random number data register has a corresponding control register, > however it returns data regardless of the

[Qemu-devel] [PATCH v4] aspeed_scu: Implement RNG register

2018-06-13 Thread Joel Stanley
The ASPEED SoCs contain a single register that returns random data when read. This models that register so that guests can use it. The random number data register has a corresponding control register, however it returns data regardless of the state of the enabled bit, so the model follows this beh