Re: [Qemu-devel] [PATCH v4 04/20] ppc/pnv: add a PIR handler to PnvChip

2016-10-10 Thread Cédric Le Goater
On 10/07/2016 06:34 AM, David Gibson wrote: > On Mon, Oct 03, 2016 at 09:24:40AM +0200, Cédric Le Goater wrote: >> The Processor Identification Register (PIR) is a register that holds a >> processor identifier which is used for bus transactions (XSCOM) and >> for processor differentiation in

Re: [Qemu-devel] [PATCH v4 04/20] ppc/pnv: add a PIR handler to PnvChip

2016-10-06 Thread David Gibson
On Mon, Oct 03, 2016 at 09:24:40AM +0200, Cédric Le Goater wrote: > The Processor Identification Register (PIR) is a register that holds a > processor identifier which is used for bus transactions (XSCOM) and > for processor differentiation in multiprocessor systems. It also used > in the

[Qemu-devel] [PATCH v4 04/20] ppc/pnv: add a PIR handler to PnvChip

2016-10-03 Thread Cédric Le Goater
The Processor Identification Register (PIR) is a register that holds a processor identifier which is used for bus transactions (XSCOM) and for processor differentiation in multiprocessor systems. It also used in the interrupt vector entries (IVE) to identify the thread serving the interrupts. P9