This series implements the reading and writing of Special Purpose Registers in PPC's gdbstub.
How it works generally [1]: GDB asks for the target.xml file which contains the target description along with the list of available feature XMLs. GDB then asks for each of the XML files in sequence. The XML files contain a list of registers descriptions: <reg name="msr" bitsize="64" type="uint64"/> When the user tries to access a register, GDB reads the XML file in sequence and sends QEMU the number of the register. This number is sequential across all feature files. The index provided by GDB must be converted by QEMU to match QEMU's internal representation. A set of callbacks are implemented to read/write the register. Note about endianness: GDB remote protocol defines that registers should be sent in target (guest) byte order. It will store the value in memory without regard to endianness and later use what it thinks is the target endianness to choose a byte order for printing. This means that the `show endian` option in GDB should match the guest's current endianness for the values to display properly. Notice that GDB and QEMU could be running in machines of opposite endianness. https://sourceware.org/gdb/current/onlinedocs/gdb/Target-Descriptions.html v1 -> v2: - patch 1: explicitly store the gdb_id and add comment explaining why we need it - patch 2: use gdb_id to find the correct env->spr array's index https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg00648.html v2 -> v3: - patch 2: move gdb_register_coprocessor call from patch 3 so that all patches build independently https://lists.gnu.org/archive/html/qemu-devel/2019-01/msg02939.html v3 -> v4: - patch 1: move gdb_spr_xml into PowerPCCPUClass so that it is generated only once for all CPUs http://lists.nongnu.org/archive/html/qemu-ppc/2019-01/msg00357.html v4 -> v5: - squash all 3 patches - use g_string_append() instead of g_string_append_printf() where possible - free the g_ascii_strdown() string - fix uninitialized variable - use POWERPC_CPU_GET_CLASS with CPUState Regarding the endianness discussion, continue providing the registers in the target endianness as GBD currently requires this. http://lists.nongnu.org/archive/html/qemu-ppc/2019-01/msg00498.html Fabiano Rosas (1): target/ppc: Enable reporting of SPRs to GDB target/ppc/cpu-qom.h | 4 +++ target/ppc/cpu.h | 5 +++ target/ppc/gdbstub.c | 61 ++++++++++++++++++++++++++++++++ target/ppc/translate_init.inc.c | 62 +++++++++++++++++++++++++++++++-- 4 files changed, 130 insertions(+), 2 deletions(-) -- 2.17.1