Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 1519683480-33201-1-git-send-email-...@sifive.com
Subject: [Qemu-devel] [PATCH v7 00/23] RISC-V QEMU Port Submission
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
On 02/26/2018 04:24 PM, Michael Clark wrote:
I've pushed a signed tag which includes the cover letter for the pull
request.
https://github.com/riscv/riscv-qemu/releases/tag/riscv-qemu-upstream-v7
Apologies. I'm not exactly sure how to format a pull request email.
I use:
$ git request-pull or
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1519683480-33201-1-git-send-email-...@sifive.com
Subject: [Qemu-devel] [PATCH v7 00/23] RISC-V QEMU Port Submission
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
I've pushed a signed tag which includes the cover letter for the pull
request.
https://github.com/riscv/riscv-qemu/releases/tag/riscv-qemu-upstream-v7
Apologies. I'm not exactly sure how to format a pull request email.
On Tue, Feb 27, 2018 at 11:17 AM, Michael Clark wrote:
> QEMU RISC-V Emulat
QEMU RISC-V Emulation Support (RV64GC, RV32GC)
With this reelase we have contacted all contributors and have received
agreement to re-license their work as GPLv2+. This release also updates
linux-user/riscv/termbits.h which should fix S390 builds. The spike_v1.9
machine has been renamed to spike_v
